Cadence 南京职位来袭，欢迎你加入！
热招岗位
01
数字后端设计工程师
工作内容：
1.In charge of IP and SoC physical design and Implementation
2.Strong experiences in the digital implementation domain including Floorplan, P&R, Physical verification, DFM
3.C/C++/perl/tcl/csh/python,UNIX,Linux experience are plus
02
DFT/Synsthesis/STA工程师
工作内容：
1.Complete design implementation flows and related QA signoff for Serdes IP: Synthesis, CTS, STA, DFT/ATPG, LEC/CLP, etc
2. Proficiency in design flows
3. Support backend team to complete chip implementation signoff and tape out
03
高级技术市场经理
工作内容：
1. Definition and promotion of products that will result in sustainable growth within product line responsibilities
2. Monitor and analyze market trends of end-product markets
3. Creation of strategic and tactical marketing plans
4. New product rollouts & launch
5. TAM/SAM analysis
04
模拟版图工程师
工作内容：
1. Works closely with the design engineering team to implement high-speed Serdes IP layout such as PLL, Transmitter, Receiver, Bandgap, ADC, DDRIO, etc
2. Create, review, verify and deliver high quality layout that conforms to all design requirements
3. Independently debug complex design and PDK issues
4. More than 5 years experience in analog/mixed-signal layout
05
验证工程师
工作内容：
1. Responsible for IP/SoC verification based on metric driven methodology
2. Developing and using verification components(UVC, VIP,AVIP, Specman)
3. Developing constrained random verification environment, responsible for coverage closure
06
AE工程师
工作内容：
1. 对客户需求进行评估，并给出合理技术方案
2. 售前售后技术支持
3. 三年以上IC设计经验，有高速接口IP（DDR，Serdes）设计或使用经验者优先
关于Cadence
Cadence是一家电子设计自动化(EDA)与半导体知识产权(IP)的领先供应商。我们的定制/模拟工具帮助工程师设计构成芯片级系统(SoCs)芯片的晶体管、标准单元和IP模块。我们的数字工具可对千兆级、千兆赫兹及最新半导体工艺节点的SoC进行自动化设计和验证。我们的IC封装和 PCB工具可实现完整的电路板和子系统的设计。
Cadence还提供用于存储器、接口协议、模拟/混合信号组件和专业处理器设计IP和验证IP不断增长的产品。在系统层面，Cadence提供一个集成的硬件/软件套件协同开发平台。总之，Cadence的创新技术在创造改变生活的重大电子产品中起着至关重要的作用。
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相关合作，请联系：
场地合作：025-56679937
高端讲坛：025-56679934